The present invention relates generally to data processing systems, and more specially, to a method, system and computer program product for performing a repair operation in a computer system using arrays having array cells.
Storage arrays on a microprocessor chip, such as static random access memories (SRAMs) or embedded dynamic random access memories (EDRAMs), are usually tested with special array test procedures (ABIST—“array built-in self-test”) before running functional tests. To improve yield, such array structures often include redundancy to allow repairing certain types of manufacturing defects. One of the main purposes of ABIST is to determine this repair information.
However, even the best testing cannot cover all usage scenarios. Some types of defects tend to escape systematic testing. To avoid system failures, systems have to be built to deal with such array defects (e.g. by implementing parity to detect a problem and prevent error propagation). Ideally, array defects that escaped testing but are detected during functional use should also get added to the array repair information, the same way as array defects found during ABIST testing.
If the error detection scheme includes a method that identifies the exact location of the failing bit (e.g., certain types of error correcting code (ECC)), a “perfect” repair is possible. This does not work for a simple parity scheme, where essentially all the information that is available is which parity group was failing, and the location of that parity group within the array; but not the exact bit that failed. Even if redundancy were available, it would be prohibitively expensive to replace a whole parity group with redundant array cells.